In high speed switching of digital signals a switching system, typically part of a switch card, is connected to a backplane. Multiple line cards that each include a plurality of Ethernet connection ports are also connected to the backplane. The Ethernet ports provide connectivity to a vast array of digital devices, e.g., computers, printers, and the like, on a typical computer network. The switching system provides high speed switching of the digital signals to and from the digital devices connected to the line cards.
A typical conventional switching system includes, inter alia, a transmitter and a receiver on an IC that are connected to the backplane. The line card, or other similar device, similarly includes a transmitter and receiver connected to a backplane.
A lane includes two logical connections. It includes both the connection from the transmitter of the switching system on the switch card to the backplane and to the receiver on the line card, and the connection from the transmitter on the line card to the backplane and to the receiver on the switching system on the switch card. A single lane allows transmitting data from the switch card to the line card and transmitting data from the line card to the switch card simultaneously. These are commonly called the ingress (inbound) and egress (outbound) sides of the lane. Data is typically transmitted out to the line card on the egress side and data is received from the line card on the ingress side. Therefore, in order for the line card, or similar device, to function properly with the switch card, the egress side of the lane must match the receiver on the line card, or similar device, and the ingress side of the lane must match the transmitter on the line card. Hence, if the receiver and transmitter of the line card do not match the appropriate egress and ingress sides of the lane the devices may still function properly but communication will fail.
Typical prior art lane reversal switching systems that attempt to overcome this problem utilize two ICs that each includes a transmitter and a receiver. The designs utilize one transmitter/receiver pair on one chip connected to the egress and ingress sides of the lane that match one type of device and utilize the other transmitter/receiver pair on the other chip that are connected to opposite sides of the lane to provide connectivity to another type of device that has the configuration of its transmitter and receiver reversed.
Because the transmitter and receiver on one of the two chips are connected to opposite sides of the lane from the transmitter and receiver on the other chip, two nodes exist at the connection point between the two sides of the lane.
In operation, the DC impedance seen looking into these nodes is less than expected, e.g., half the expected impedance. The result of the DC impedance mismatch is a reduced signal amplitude strength seen at the receiver.
Associated with each of the transmitters and receivers on the ICs and their terminating resistances are bond wires that are connected to package traces. Outside each IC or chip, card traces connect the package traces for the respective transmitters and receivers to a connector that connects to the backplane. At high frequency AC, e.g., 3.2 Gbits/sec, the transition time for a pulse is approximately 100 picoseconds, which approaches the travel time of the pulse through the package traces and card traces. At such high frequencies the card traces and package traces behave like transmission lines and have a characteristic impedance associated with them. Therefore, the high frequency AC impedance seen looking into the two nodes on the two sides of the lane is less than the expected high frequency AC impedance. The result of this high frequency AC impedance mismatch is reflections at two nodes. When the design includes a terminating resistance connected to each transmitter and each receiver of the transmitter/receiver pairs, then a reduced high frequency signal amplitude is received by the active receiver. If the design eliminates the terminating resistances connected to the receivers of the transmitter/receiver pairs on the ICs to provide DC impedance matching, then the high frequency impedance mismatch results in reflections not only at the nodes on the sides of the lane, but also at the receivers of the transmitter/receiver pairs on the ICs. These additional high frequency reflections at the receivers cause pulse edge distortion.